1. Technical Field
This disclosure relates to a semiconductor integrated circuit, and more particularly, to an address delay circuit of a semiconductor memory apparatus.
2. Related Art
In general, an address delay circuit of a typical semiconductor memory apparatus receives an external address which is received from an outside, and outputs an internal address.
FIG. 1 is a configuration diagram illustrating a conventional address delay circuit of a semiconductor memory apparatus. The typical address delay circuit of FIG. 1 outputs three external addresses Address<0:2> as three internal addresses Address_dl<0:2> after 5 cycles of a clock CLK elapse.
Referring to FIG. 1, the typical address delay circuit of a semiconductor memory apparatus may include first through fifteenth flip-flops 1 through 15.
The first through fifth flip-flops 1 through 5 may be coupled in series. The first flip-flop 1 may receive a first external address Address<0>, and the fifth flip-flop 5 may output a first internal address Address_dl<0>.
The sixth through tenth flip-flops 6 through 10 may be coupled in series. The sixth flip-flop 6 may receive a second external address Address<1>, and the tenth flip-flop 10 may output a second internal address Address_dl<1>.
The eleventh through fifteenth flip-flops 11 through 15 may be coupled in series. The eleventh flip-flop 11 may receive a third external address Address<2>, and the fifteenth flip-flop 15 may output a third internal address Address_dl<2>. Each of the first through fifteenth flip-flops 1 through 15 may perform inputting, storing and outputting operations in response to the clock CLK.
A problem with conventional address delay circuits is the necessary area and current consumption increase needed as the number of external addresses to be received by a semiconductor memory apparatus increases and a delay time is lengthened. As can be seen from FIG. 1, in the typical address delay circuit of a typical semiconductor memory apparatus, a predetermined number of flip-flops which are coupled in series are needed to delay one external address and output one internal address. In such a type of conventional address delay circuit of a semiconductor memory apparatus, as the number of external addresses to be received by a semiconductor memory apparatus increases and a delay time is lengthened, an increased number of flip-flops are needed, by which a necessary area and current consumption increase.